4.9: Detector electronics chain

This deliverable report D4.9 – Detector electronics chain describes the completion of a readout electronics chain for the NMX prototype detector, currently developed jointly by ESS and CERN within Work Package 4 Task 4.1. It contains information about the already available hardware used as a starting point for dedicated developments and the reasons why these components were selected. The components are in particular the VMM front-end ASIC developed within the ATLAS New Small Wheel upgrade project and the Scalable Readout System of the RD51 Collaboration1.

The VMM ASIC features high readout rates, low electronic noise, excellent configuration possibilities and easy availability. The Scalable Readout System (SRS) is also freely available and allows for the implementation of new front-end ASICs within the timescale of this project. Moreover, as the name suggests, this readout system can be scaled from small detectors used during the development phase to the final prototype (to be delivered at the end of the project), or even several and larger detectors like foreseen at the NMX instrument.

Several new hardware components and FPGA firmware have been developed in order to implement the VMM Application Specific Integrated Circuit (ASIC) into the Scalable Readout System. The system shows reliable operation in laboratory tests as well as in a first test beam at the R2D2 beamline at IFE, Norway.
Towards the end of the BrightnESS project, improvements to the system will be implemented to increase the readout rate and provide a user-friendly system with online data monitoring. It should be noted that there is close collaborative work between BrightnESS WP4 and WP5 on this online data monitoring.

DOI: https://doi.org/10.17199/BRIGHTNESS.D4.9